Scaling down semiconductor devices, such as metal oxide semiconductor (MOS) transistors, to deep sub-micron dimensions has required changes in gate sidewall structures and materials from all silicon oxide, to all silicon nitride, to a combination of silicon oxide and silicon nitride sidewalls. To increase the space between gate structures for a metal silicide source drain electrode and a pre-metal layer dielectric (PMD), the silicon nitride and oxide sidewalls are trimmed back after dopant implantation. Unfortunately, devices produced in this fashion have a higher than desired run-to-run variability in current leakage.
Accordingly, what is needed is a method for manufacturing semiconductor devices that that addresses the drawbacks of the prior art methods and devices.